
2010-2012 Microchip Technology Inc.
DS41417B-page 169
PIC16(L)F722A/723A
FIGURE 17-11:
I2C SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
SS
PI
F
BF
Re
ce
ive
Da
ta
Byte
R/W
R
e
ce
iv
e
F
irs
tB
yte
of
A
ddr
ess
Cle
ar
e
d
in
so
ftwa
re
C
lear
ed
in
so
ftw
ar
e
R
e
cei
ve
S
econd
B
yte
o
fA
ddre
ss
C
le
ar
ed
by
har
d
w
a
re
wh
e
n
SS
P
A
DD
is
u
p
d
a
te
d
with
lo
w
b
yte
o
fa
d
dr
e
ss
UA
C
lo
ck
is
h
e
ld
lo
w
u
n
til
update
of
S
P
A
D
has
ta
ken
pl
ace
U
A
is
set
indi
ca
ting
that
the
S
P
A
D
needs
to
be
u
pdate
d
UA
is
se
tin
d
ica
tin
g
that
S
P
A
DD
nee
ds
to
be
u
pdate
d
Cle
ar
e
d
b
yh
a
rd
wa
re
wh
e
n
SSP
ADD
is
u
p
d
ate
d
with
h
ig
h
by
te
o
fad
d
res
s
SS
PBUF
is
wr
itt
e
n
w
ith
conten
ts
of
S
P
S
R
D
ummy
r
ead
of
S
P
B
U
F
to
clear
B
F
flag
CKP
Re
ce
ive
Da
ta
B
yte
B
u
sm
a
ster
sends
S
top
condi
tion
ACK
Cle
a
re
d
in
so
ftwa
re
Cl
ea
re
din
so
ftwa
re
SSP
O
V
S
SPO
V
is
s
e
t
b
e
ca
us
e
SS
PBUF
is
still
fu
ll.
ACK
is
n
o
tse
nt
.
Clo
ck
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
A
D
has
ta
ken
pl
ac
e
SD
A
SC
L
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
7
8
9
P
1
0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D1
D0
AC
K
ACK
D2
6
ACK
1
2
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
D0
D2
6
AC
K
0